- Title
- A high-level architecture for efficient packet trace analysis on gpu co-processors
- Creator
- Nottingham, Alastair, Irwin, Barry V W
- Subject
- To be catalogued
- Date
- 2013
- Type
- text
- Type
- article
- Identifier
- http://hdl.handle.net/10962/429572
- Identifier
- vital:72623
- Identifier
- 10.1109/ISSA.2013.6641052
- Description
- This paper proposes a high-level architecture to support efficient, massively parallel packet classification, filtering and analysis using commodity Graphics Processing Unit (GPU) hardware. The proposed architecture aims to provide a flexible and efficient parallel packet processing and analysis framework, supporting complex programmable filtering, data mining operations, statistical analysis functions and traffic visualisation, with minimal CPU overhead. In particular, this framework aims to provide a robust set of high-speed analysis functionality, in order to dramatically reduce the time required to process and analyse extremely large network traces. This architecture derives from initial research, which has shown GPU co-processors to be effective in accelerating packet classification to up to tera-bit speeds with minimal CPU overhead, far exceeding the bandwidth capacity between standard long term storage and the GPU device. This paper provides a high-level overview of the proposed architecture and its primary components, motivated by the results of prior research in the field.
- Format
- 7 pages, pdf
- Language
- English
- Relation
- Information Security for South Africa (ISSA), Nottingham, A. and Irwin, B., 2013, August. A high-level architecture for efficient packet trace analysis on gpu co-processors. In 2013 Information Security for South Africa (pp. 1-8). IEEE, Information Security for South Africa (ISSA) volume 2013 number 1 1 8 2015 2330-9881
- Rights
- Publisher
- Rights
- Use of this resource is governed by the terms and conditions of the IEEE Xplore Terms of Use Statement (https://ieeexplore.ieee.org/Xplorehelp/overview-of-ieee-xplore/terms-of-use)
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- Visitors: 18
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Collections
Irwin, Barry V W (Prof)
RU Department of Computer Science
SDG 09. Industry, Innovation and Infrastructure
| Thumbnail | File | Description | Size | Format | |||
|---|---|---|---|---|---|---|---|
| View Details | SOURCE1 | A high-level architecture for efficient packet trace analysis on gpu co-processors.pdf | 646 KB | Adobe Acrobat PDF | View Details |