Blended Agile Learning of Computer Architecture under COVID
- Authors: Machanick, Philip
- Date: 2023
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/439141 , vital:73550 , https://www.researchgate.net/profile/Grant-Ooster-wyk/publication/375547243_Beyond_the_Hype_A_Cautionary_Tale_of_ChatGPT_in_the_Programming_Classroom/links/654e3009b1398a779d76a75e/Beyond-the-Hype-A-Cautionary-Tale-of-ChatGPT-in-the-Programming-Classroom.pdf#page=45
- Description: The COVID-19 pandemic presented unique challenges. 2021 was an interesting year because we had overcome the worst of the teething problems of remote learning but were able to resume some in-person activities. I present experiences from a second-year computer architecture course that I have taught since 2014 to illustrate that some lessons from operating under pandemic conditions can apply to running courses under more normal conditions. 2021 was an interesting year because we reintroduced in-person pracs partway through this course, allowing students to reflect on the difference this made. Reflection on what did and did not work in the course points to possible improvements in pedagogy in more “normal” times. In isolation, the very positive feedback in a course survey may be flattering but there are useful insights to be drawn from what worked. Drawing on ideas from the social construction model of education, where students should be actively involved in learning, and agile software development, results in some insights that may generalize. The kind of feedback that is part of agile development can be layered on top of formative assessment. Empathy with difficulties faced by a class can make a class more involved in the strategy for course delivery. In 2022, without COVID constraints, some of the lessons were applied with positive outcomes.
- Full Text:
- Authors: Machanick, Philip
- Date: 2023
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/439141 , vital:73550 , https://www.researchgate.net/profile/Grant-Ooster-wyk/publication/375547243_Beyond_the_Hype_A_Cautionary_Tale_of_ChatGPT_in_the_Programming_Classroom/links/654e3009b1398a779d76a75e/Beyond-the-Hype-A-Cautionary-Tale-of-ChatGPT-in-the-Programming-Classroom.pdf#page=45
- Description: The COVID-19 pandemic presented unique challenges. 2021 was an interesting year because we had overcome the worst of the teething problems of remote learning but were able to resume some in-person activities. I present experiences from a second-year computer architecture course that I have taught since 2014 to illustrate that some lessons from operating under pandemic conditions can apply to running courses under more normal conditions. 2021 was an interesting year because we reintroduced in-person pracs partway through this course, allowing students to reflect on the difference this made. Reflection on what did and did not work in the course points to possible improvements in pedagogy in more “normal” times. In isolation, the very positive feedback in a course survey may be flattering but there are useful insights to be drawn from what worked. Drawing on ideas from the social construction model of education, where students should be actively involved in learning, and agile software development, results in some insights that may generalize. The kind of feedback that is part of agile development can be layered on top of formative assessment. Empathy with difficulties faced by a class can make a class more involved in the strategy for course delivery. In 2022, without COVID constraints, some of the lessons were applied with positive outcomes.
- Full Text:
The Case for a Cray on a Chip
- Authors: Machanick, Philip
- Date: 2023
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/439277 , vital:73561 , https://www.researchgate.net/profile/Siphamandla-Mncu-be/publication/375376322_Shadow_Information_Technology_in_the_Advent_of_Open_Educational_Resources/links/65485042ce88b87031c92188/Shadow-Information-Technology-in-the-Advent-of-Open-Educational-Resources.pdf#page=22
- Description: Moore’s Law is usually interpreted as a prediction of how many transistors you can buy for the same money at some future date. It can also be interpreted as how long you need to wait until a given number of transistors falls below a target price. An example of this reverse-application of Moore’s Law is transitions such as the emergence of microprocessors competitive with traditional larger-scale computers and the emergence of smartphones. Since the late 1990s, it has become increasingly common for growth in transistors to equate to more CPUs (cores) per die. Recent designs have over 50 billion transistors and far more potential parallelism than can be supported by memory. I argue the case for a rebalancing of design goals with a much larger, faster on-chip memory and a CPU that is designed around this memory system. The proposal: a Cray-class vector CPU on a die with 1 Gibyte of static RAM, or Crayon (for Cray on a chip). The kind of organization classically used by Cray vector supercomputers is feasible to achieve on a single chip. I argue that a design like this can use the available memory bandwidth, as opposed to over-CPU designs with a large number of cores and GPU threads that are memory limited and propose how such a design could be used.
- Full Text:
- Authors: Machanick, Philip
- Date: 2023
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/439277 , vital:73561 , https://www.researchgate.net/profile/Siphamandla-Mncu-be/publication/375376322_Shadow_Information_Technology_in_the_Advent_of_Open_Educational_Resources/links/65485042ce88b87031c92188/Shadow-Information-Technology-in-the-Advent-of-Open-Educational-Resources.pdf#page=22
- Description: Moore’s Law is usually interpreted as a prediction of how many transistors you can buy for the same money at some future date. It can also be interpreted as how long you need to wait until a given number of transistors falls below a target price. An example of this reverse-application of Moore’s Law is transitions such as the emergence of microprocessors competitive with traditional larger-scale computers and the emergence of smartphones. Since the late 1990s, it has become increasingly common for growth in transistors to equate to more CPUs (cores) per die. Recent designs have over 50 billion transistors and far more potential parallelism than can be supported by memory. I argue the case for a rebalancing of design goals with a much larger, faster on-chip memory and a CPU that is designed around this memory system. The proposal: a Cray-class vector CPU on a die with 1 Gibyte of static RAM, or Crayon (for Cray on a chip). The kind of organization classically used by Cray vector supercomputers is feasible to achieve on a single chip. I argue that a design like this can use the available memory bandwidth, as opposed to over-CPU designs with a large number of cores and GPU threads that are memory limited and propose how such a design could be used.
- Full Text:
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