NFComms: A synchronous communication framework for the CPU-NFP heterogeneous system
- Authors: Pennefather, Sean
- Date: 2020
- Subjects: Network processors , Computer programming , Parallel processing (Electronic computers) , Netronome
- Language: English
- Type: text , Thesis , Doctoral , PhD
- Identifier: http://hdl.handle.net/10962/144181 , vital:38318
- Description: This work explores the viability of using a Network Flow Processor (NFP), developed by Netronome, as a coprocessor for the construction of a CPU-NFP heterogeneous platform in the domain of general processing. When considering heterogeneous platforms involving architectures like the NFP, the communication framework provided is typically represented as virtual network interfaces and is thus not suitable for generic communication. To enable a CPU-NFP heterogeneous platform for use in the domain of general computing, a suitable generic communication framework is required. A feasibility study for a suitable communication medium between the two candidate architectures showed that a generic framework that conforms to the mechanisms dictated by Communicating Sequential Processes is achievable. The resulting NFComms framework, which facilitates inter- and intra-architecture communication through the use of synchronous message passing, supports up to 16 unidirectional channels and includes queuing mechanisms for transparently supporting concurrent streams exceeding the channel count. The framework has a minimum latency of between 15.5 μs and 18 μs per synchronous transaction and can sustain a peak throughput of up to 30 Gbit/s. The framework also supports a runtime for interacting with the Go programming language, allowing user-space processes to subscribe channels to the framework for interacting with processes executing on the NFP. The viability of utilising a heterogeneous CPU-NFP system for use in the domain of general and network computing was explored by introducing a set of problems or applications spanning general computing, and network processing. These were implemented on the heterogeneous architecture and benchmarked against equivalent CPU-only and CPU/GPU solutions. The results recorded were used to form an opinion on the viability of using an NFP for general processing. It is the author’s opinion that, beyond very specific use cases, it appears that the NFP-400 is not currently a viable solution as a coprocessor in the field of general computing. This does not mean that the proposed framework or the concept of a heterogeneous CPU-NFP system should be discarded as such a system does have acceptable use in the fields of network and stream processing. Additionally, when comparing the recorded limitations to those seen during the early stages of general purpose GPU development, it is clear that general processing on the NFP is currently in a similar state.
- Full Text:
- Date Issued: 2020
- Authors: Pennefather, Sean
- Date: 2020
- Subjects: Network processors , Computer programming , Parallel processing (Electronic computers) , Netronome
- Language: English
- Type: text , Thesis , Doctoral , PhD
- Identifier: http://hdl.handle.net/10962/144181 , vital:38318
- Description: This work explores the viability of using a Network Flow Processor (NFP), developed by Netronome, as a coprocessor for the construction of a CPU-NFP heterogeneous platform in the domain of general processing. When considering heterogeneous platforms involving architectures like the NFP, the communication framework provided is typically represented as virtual network interfaces and is thus not suitable for generic communication. To enable a CPU-NFP heterogeneous platform for use in the domain of general computing, a suitable generic communication framework is required. A feasibility study for a suitable communication medium between the two candidate architectures showed that a generic framework that conforms to the mechanisms dictated by Communicating Sequential Processes is achievable. The resulting NFComms framework, which facilitates inter- and intra-architecture communication through the use of synchronous message passing, supports up to 16 unidirectional channels and includes queuing mechanisms for transparently supporting concurrent streams exceeding the channel count. The framework has a minimum latency of between 15.5 μs and 18 μs per synchronous transaction and can sustain a peak throughput of up to 30 Gbit/s. The framework also supports a runtime for interacting with the Go programming language, allowing user-space processes to subscribe channels to the framework for interacting with processes executing on the NFP. The viability of utilising a heterogeneous CPU-NFP system for use in the domain of general and network computing was explored by introducing a set of problems or applications spanning general computing, and network processing. These were implemented on the heterogeneous architecture and benchmarked against equivalent CPU-only and CPU/GPU solutions. The results recorded were used to form an opinion on the viability of using an NFP for general processing. It is the author’s opinion that, beyond very specific use cases, it appears that the NFP-400 is not currently a viable solution as a coprocessor in the field of general computing. This does not mean that the proposed framework or the concept of a heterogeneous CPU-NFP system should be discarded as such a system does have acceptable use in the fields of network and stream processing. Additionally, when comparing the recorded limitations to those seen during the early stages of general purpose GPU development, it is clear that general processing on the NFP is currently in a similar state.
- Full Text:
- Date Issued: 2020
Design and evaluation of bulk data transfer extensions for the NFComms framework
- Bradshaw, Karen L, Irwin, Barry V W, Pennefather, Sean
- Authors: Bradshaw, Karen L , Irwin, Barry V W , Pennefather, Sean
- Date: 2019
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/430369 , vital:72686 , https://hdl.handle.net/10520/EJC-1d75c01e79
- Description: We present the design and implementation of an indirect messaging extension for the existing NFComms framework that provides communication between a network flow processor and host CPU. This extension addresses the bulk throughput limitations of the framework and is intended to work in conjunction with existing communication mediums. Testing of the framework extensions shows an increase in throughput performance of up to 268 that of the current direct message passing framework at the cost of increased single message latency of up to 2. This trade-off is considered acceptable as the proposed extensions are intended for bulk data transfer only while the existing message passing functionality of the framework is preserved and can be used in situations where low latency is required for small messages.
- Full Text:
- Date Issued: 2019
- Authors: Bradshaw, Karen L , Irwin, Barry V W , Pennefather, Sean
- Date: 2019
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/430369 , vital:72686 , https://hdl.handle.net/10520/EJC-1d75c01e79
- Description: We present the design and implementation of an indirect messaging extension for the existing NFComms framework that provides communication between a network flow processor and host CPU. This extension addresses the bulk throughput limitations of the framework and is intended to work in conjunction with existing communication mediums. Testing of the framework extensions shows an increase in throughput performance of up to 268 that of the current direct message passing framework at the cost of increased single message latency of up to 2. This trade-off is considered acceptable as the proposed extensions are intended for bulk data transfer only while the existing message passing functionality of the framework is preserved and can be used in situations where low latency is required for small messages.
- Full Text:
- Date Issued: 2019
Exploration and design of a synchronous message passing framework for a CPU-NPU heterogeneous architecture
- Pennefather, Sean, Bradshaw, Karen L, Irwin, Barry V W
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429537 , vital:72620 , https://ieeexplore.ieee.org/abstract/document/8425384
- Description: In this paper we present the development of a framework for communication between an NPU (network processing unit) and CPU through synchronous message passing that is compliant with the synchronous communication events of the CSP formalisms. This framework is designed to be used for passing generic information between application components operating on both architectures and is intended to operate in conjunction with existing datapaths present on the NPU which in turn are responsible for network traffic transmission. An investigation of different message passing topologies is covered before the proposed message passing fabric is presented. As a proof of concept, an initial implementation of the fabric is developed and tested to determine its viability and correctness. Through testing it is shown that the implemented framework operates as intended. However, it is noted the throughput of the exploratory implementation is not considered suitable for high-performance applications and further evaluation is required.
- Full Text:
- Date Issued: 2018
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429537 , vital:72620 , https://ieeexplore.ieee.org/abstract/document/8425384
- Description: In this paper we present the development of a framework for communication between an NPU (network processing unit) and CPU through synchronous message passing that is compliant with the synchronous communication events of the CSP formalisms. This framework is designed to be used for passing generic information between application components operating on both architectures and is intended to operate in conjunction with existing datapaths present on the NPU which in turn are responsible for network traffic transmission. An investigation of different message passing topologies is covered before the proposed message passing fabric is presented. As a proof of concept, an initial implementation of the fabric is developed and tested to determine its viability and correctness. Through testing it is shown that the implemented framework operates as intended. However, it is noted the throughput of the exploratory implementation is not considered suitable for high-performance applications and further evaluation is required.
- Full Text:
- Date Issued: 2018
Extending the NFComms framework for bulk data transfers
- Pennefather, Sean, Bradshaw, Karen L, Irwin, Barry V W
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/430152 , vital:72669 , https://doi.org/10.1145/3278681.3278686
- Description: In this paper we present the design and implementation of an indirect messaging extension for the existing NFComms framework that pro-vides communication between a network flow processor and host CPU. This extension addresses the bulk throughput limitations of the frame-work and is intended to work in conjunction with existing communication mediums. Testing of the framework extensions shows an increase in throughput performance of up to 300× that of the current direct mes-sage passing framework at the cost of increased single message laten-cy of up to 2×. This trade-off is considered acceptable as the proposed extensions are intended for bulk data transfer only while the existing message passing functionality of the framework is preserved and can be used in situations where low latency is required for small messages.
- Full Text:
- Date Issued: 2018
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/430152 , vital:72669 , https://doi.org/10.1145/3278681.3278686
- Description: In this paper we present the design and implementation of an indirect messaging extension for the existing NFComms framework that pro-vides communication between a network flow processor and host CPU. This extension addresses the bulk throughput limitations of the frame-work and is intended to work in conjunction with existing communication mediums. Testing of the framework extensions shows an increase in throughput performance of up to 300× that of the current direct mes-sage passing framework at the cost of increased single message laten-cy of up to 2×. This trade-off is considered acceptable as the proposed extensions are intended for bulk data transfer only while the existing message passing functionality of the framework is preserved and can be used in situations where low latency is required for small messages.
- Full Text:
- Date Issued: 2018
Real-time geotagging and filtering of network data using a heterogeneous NPU-CPU architecture
- Pennefather, Sean, Bradshaw, Karen L, Irwin, Barry V W
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , book
- Identifier: http://hdl.handle.net/10962/460603 , vital:75968 , ISBN 9780620810227
- Description: In this paper, we present the design and implementation of a NPU-CPU heterogeneous network monitoring application. This application allows for both filtering and monitoring operations to be performed on network traffic based on country of origin or destination of IP traffic in real-time at wire speeds up to 1 Gbit/s. This is achievable by distributing the application components to the relevant candidate architectures, leveraging the strengths of each. Communication between architectures is handled at runtime by a low latency synchronous message passing library. Testing of the implemented application indicates that the system can perform geolocation lookups on network traffic in real-time without impacting network throughput.
- Full Text:
- Date Issued: 2018
- Authors: Pennefather, Sean , Bradshaw, Karen L , Irwin, Barry V W
- Date: 2018
- Subjects: To be catalogued
- Language: English
- Type: text , book
- Identifier: http://hdl.handle.net/10962/460603 , vital:75968 , ISBN 9780620810227
- Description: In this paper, we present the design and implementation of a NPU-CPU heterogeneous network monitoring application. This application allows for both filtering and monitoring operations to be performed on network traffic based on country of origin or destination of IP traffic in real-time at wire speeds up to 1 Gbit/s. This is achievable by distributing the application components to the relevant candidate architectures, leveraging the strengths of each. Communication between architectures is handled at runtime by a low latency synchronous message passing library. Testing of the implemented application indicates that the system can perform geolocation lookups on network traffic in real-time without impacting network throughput.
- Full Text:
- Date Issued: 2018
Design and application of link: A DSL for network frame manipulation
- Pennefather, Sean, Irwin, Barry V W
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2017
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429230 , vital:72569 , https://ieeexplore.ieee.org/abstract/document/8251774
- Description: This paper describes the design and application of Link, a Domain Specific Language (DSL) targeting the development of network applications focused on traffic manipulation at the frame level. The development of Link is described through the identification and evaluation of intended applications and an example translator is implemented to target the FRAME board which was developed in conjunction with this research. Four application examples are then provided to help describe the feasibility of Link when used in conjunction with the implemented translator.
- Full Text:
- Date Issued: 2017
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2017
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429230 , vital:72569 , https://ieeexplore.ieee.org/abstract/document/8251774
- Description: This paper describes the design and application of Link, a Domain Specific Language (DSL) targeting the development of network applications focused on traffic manipulation at the frame level. The development of Link is described through the identification and evaluation of intended applications and an example translator is implemented to target the FRAME board which was developed in conjunction with this research. Four application examples are then provided to help describe the feasibility of Link when used in conjunction with the implemented translator.
- Full Text:
- Date Issued: 2017
Design of a Message Passing Model for Use in a Heterogeneous CPU-NFP Framework for Network Analytics. Southern Africa Telecommunication Networks and Applications Conference (SATNAC) 2017, 3-10 September 2017
- Pennefather, Sean, Bradshaw, Karen L, Barry, Irwin V W
- Authors: Pennefather, Sean , Bradshaw, Karen L , Barry, Irwin V W
- Date: 2017
- Subjects: To be catalogued
- Language: English
- Type: text , book
- Identifier: http://hdl.handle.net/10962/460011 , vital:75884 , ISBN 9780620767569 , http://dx.doi.org/10.18489/sacj.v31i2.692
- Description: Currently, network analytics requires direct access to network packets, normally through a third-party application, which means that obtaining realtime results is difficult. We propose the NFP-CPU heterogeneous framework to allow parts of applications written in the Go programming language to be executed on a Network Flow Processor (NFP) for enhanced performance. This paper explores the need and feasibility of implementing a message passing model for data transmission between the NFP and CPU, which is the crux of such a heterogeneous framework. Architectural differences between the two domains are highlighted within this context and we present a solution to bridging these differences.
- Full Text:
- Date Issued: 2017
- Authors: Pennefather, Sean , Bradshaw, Karen L , Barry, Irwin V W
- Date: 2017
- Subjects: To be catalogued
- Language: English
- Type: text , book
- Identifier: http://hdl.handle.net/10962/460011 , vital:75884 , ISBN 9780620767569 , http://dx.doi.org/10.18489/sacj.v31i2.692
- Description: Currently, network analytics requires direct access to network packets, normally through a third-party application, which means that obtaining realtime results is difficult. We propose the NFP-CPU heterogeneous framework to allow parts of applications written in the Go programming language to be executed on a Network Flow Processor (NFP) for enhanced performance. This paper explores the need and feasibility of implementing a message passing model for data transmission between the NFP and CPU, which is the crux of such a heterogeneous framework. Architectural differences between the two domains are highlighted within this context and we present a solution to bridging these differences.
- Full Text:
- Date Issued: 2017
Design of a Configurable Embedded Network Tap Flow Generation using NetFlow v9 and IPFIX Formats
- Pennefather, Sean, Irwin, Barry V W
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2016
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427756 , vital:72460 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622779_Design_of_a_Configurable_Embedded_Network_Tap_Flow_Generation_using_NetFlow_v9_and_IPFIX_Formats/links/5b9a19f2299bf14ad4d6a591/Design-of-a-Configurable-Embedded-Network-Tap-Flow-Generation-using-NetFlow-v9-and-IPFIX-Formats.pdf
- Description: This paper describes the design of a $200 hardware apparatus capable of passively monitoring network transmission at wire speeds of 100Mbit/s and generating NetFlow v9 or IPFIX compliant network flows for a downstream monitoring infrastructure. Testing of the apparatus hardware confirmed no network disruptions regardless of operational or power state while still being capable of correctly monitoring network traffic when configured. System testing under situations of heavy load confirmed apparatus capability at monitoring network traffic and correct generation of network flows compliant with either NetFlow v9 or IPFIX standards.
- Full Text:
- Date Issued: 2016
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2016
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427756 , vital:72460 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622779_Design_of_a_Configurable_Embedded_Network_Tap_Flow_Generation_using_NetFlow_v9_and_IPFIX_Formats/links/5b9a19f2299bf14ad4d6a591/Design-of-a-Configurable-Embedded-Network-Tap-Flow-Generation-using-NetFlow-v9-and-IPFIX-Formats.pdf
- Description: This paper describes the design of a $200 hardware apparatus capable of passively monitoring network transmission at wire speeds of 100Mbit/s and generating NetFlow v9 or IPFIX compliant network flows for a downstream monitoring infrastructure. Testing of the apparatus hardware confirmed no network disruptions regardless of operational or power state while still being capable of correctly monitoring network traffic when configured. System testing under situations of heavy load confirmed apparatus capability at monitoring network traffic and correct generation of network flows compliant with either NetFlow v9 or IPFIX standards.
- Full Text:
- Date Issued: 2016
Design and Fabrication of a Low Cost Traffic Manipulation Hardware Platform
- Pennefather, Sean, Irwin, Barry V W
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2015
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427873 , vital:72468 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622941_Design_and_Fabrication_of_a_Low_Cost_Traffic_Manipulation_Hardware/links/5b9a1625458515310583fc8c/Design-and-Fabrication-of-a-Low-Cost-Traffic-Manipulation-Hardware.pdf
- Description: This paper describes the design and fabrication of a dedicated hardware platform for network traffic logging and modification at a production cost of under $300. The context of the device is briefly discussed before characteristics relating to hardware development are explored. The paper concludes with three application examples to show some to the potential functionality of the platform. Testing of the device shows an average TCP throughput of 84.44 MiB/s when using the designed Ethernet modules.
- Full Text:
- Date Issued: 2015
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2015
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427873 , vital:72468 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622941_Design_and_Fabrication_of_a_Low_Cost_Traffic_Manipulation_Hardware/links/5b9a1625458515310583fc8c/Design-and-Fabrication-of-a-Low-Cost-Traffic-Manipulation-Hardware.pdf
- Description: This paper describes the design and fabrication of a dedicated hardware platform for network traffic logging and modification at a production cost of under $300. The context of the device is briefly discussed before characteristics relating to hardware development are explored. The paper concludes with three application examples to show some to the potential functionality of the platform. Testing of the device shows an average TCP throughput of 84.44 MiB/s when using the designed Ethernet modules.
- Full Text:
- Date Issued: 2015
An exploration of geolocation and traffic visualisation using network flows
- Pennefather, Sean, Irwin, Barry V W
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2014
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429597 , vital:72625 , 10.1109/ISSA.2014.6950
- Description: A network flow is a data record that represents characteristics associated with a unidirectional stream of packets transmitted between two hosts using an IP layer protocol. As a network flow only represents statistics relating to the data transferred in the stream, the effectiveness of utilizing network flows for traffic visualization to aid in cyber defense is not immediately apparent and needs further exploration. The goal of this research is to explore the use of network flows for data visualization and geolocation.
- Full Text:
- Date Issued: 2014
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2014
- Subjects: To be catalogued
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/429597 , vital:72625 , 10.1109/ISSA.2014.6950
- Description: A network flow is a data record that represents characteristics associated with a unidirectional stream of packets transmitted between two hosts using an IP layer protocol. As a network flow only represents statistics relating to the data transferred in the stream, the effectiveness of utilizing network flows for traffic visualization to aid in cyber defense is not immediately apparent and needs further exploration. The goal of this research is to explore the use of network flows for data visualization and geolocation.
- Full Text:
- Date Issued: 2014
Design of a Network Packet Processing platform
- Pennefather, Sean, Irwin, Barry V W
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2014
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427901 , vital:72472 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622772_Design_of_a_Network_Packet_Processing_platform/links/5b9a187f92851c4ba8181bd6/Design-of-a-Network-Packet-Processing-platform.pdf
- Description: This paper describes the design considerations investigated in the implementation of a prototype embedded network packet processing platform. The purpose of this system is to provide a means for researchers to process, and manipulate network traffic using an embedded standalone hardware platform, with the provision this be soft-configurable and flexible in its functionality. The performance of the Ethernet layer subsystem implemented using XMOS MCU’s is investigated. Future applications of this prototype are discussed.
- Full Text:
- Date Issued: 2014
- Authors: Pennefather, Sean , Irwin, Barry V W
- Date: 2014
- Language: English
- Type: text , article
- Identifier: http://hdl.handle.net/10962/427901 , vital:72472 , https://www.researchgate.net/profile/Barry-Ir-win/publication/327622772_Design_of_a_Network_Packet_Processing_platform/links/5b9a187f92851c4ba8181bd6/Design-of-a-Network-Packet-Processing-platform.pdf
- Description: This paper describes the design considerations investigated in the implementation of a prototype embedded network packet processing platform. The purpose of this system is to provide a means for researchers to process, and manipulate network traffic using an embedded standalone hardware platform, with the provision this be soft-configurable and flexible in its functionality. The performance of the Ethernet layer subsystem implemented using XMOS MCU’s is investigated. Future applications of this prototype are discussed.
- Full Text:
- Date Issued: 2014
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