- Title
- Exploration and design of a synchronous message passing framework for a CPU-NPU heterogeneous architecture
- Creator
- Pennefather, Sean, Bradshaw, Karen L, Irwin, Barry V W
- Subject
- To be catalogued
- Date
- 2018
- Type
- text
- Type
- article
- Identifier
- http://hdl.handle.net/10962/429537
- Identifier
- vital:72620
- Identifier
- https://ieeexplore.ieee.org/abstract/document/8425384
- Description
- In this paper we present the development of a framework for communication between an NPU (network processing unit) and CPU through synchronous message passing that is compliant with the synchronous communication events of the CSP formalisms. This framework is designed to be used for passing generic information between application components operating on both architectures and is intended to operate in conjunction with existing datapaths present on the NPU which in turn are responsible for network traffic transmission. An investigation of different message passing topologies is covered before the proposed message passing fabric is presented. As a proof of concept, an initial implementation of the fabric is developed and tested to determine its viability and correctness. Through testing it is shown that the implemented framework operates as intended. However, it is noted the throughput of the exploratory implementation is not considered suitable for high-performance applications and further evaluation is required.
- Format
- 10 pages, pdf
- Language
- English
- Relation
- IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Pennefather, S., Bradshaw, K. and Irwin, B., 2018, May. Exploration and design of a synchronous message passing framework for a CPU-NPU heterogeneous architecture. In 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 46-56). IEEE, IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) volume 2018 number 1 46 56 2018 Conference
- Rights
- Publisher
- Rights
- Use of this resource is governed by the terms and conditions of the IEEE Xplore Terms of Use Statement (https://ieeexplore.ieee.org/Xplorehelp/overview-of-ieee-xplore/terms-of-use)
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Irwin, Barry V W (Prof)
RU Department of Computer Science
Bradshaw, Karen Lee (Assoc Prof)
SDG 09. Industry, Innovation and Infrastructure
| Thumbnail | File | Description | Size | Format | |||
|---|---|---|---|---|---|---|---|
| View Details | SOURCE1 | Exploration and design of a synchronous message passing framework for a CPU-NPU heterogeneous architecture.pdf | 678 KB | Adobe Acrobat PDF | View Details |